1. Field of the Invention
The invention relates to a preparation method for an electrode and more particularly to a method suitable for the preparation of gate electrodes in various semiconductor devices.
2. Description of the Related Art
GaAs-MESFET or AlGaAs/GaAs-HEMT devices, which have conventionally been applied as a low noise amplifier for satellite broadcasting and communications in microwave band, are required to have lower parasitic capacitance by reducing gate lengths in order to improve their low noise amplification property.
Quartermicron gate electrodes are typically fabricated by lift-off process in the following manner to which FIG. 4 is referred. First, a silicon nitride film 12 and a resist film 13 are formed in this order on a GaAs substrate 11. A gate pattern is formed on the resist film 13 by electron beam lithography and used as a mask to open a hole in the silicon nitride film 12 which is then used as a mask to form a cavity 14 in the GaAs substrate 11. Thereafter, a metal deposition is conducted from the side of the silicon nitride film 12 and then the resist film 13 is removed by use of an organic solvent, leaving the deposited metal in the cavity on a corresponding portion of the substrate to the gate pattern to form a gate electrode 15. Reference numeral 16 designates the metal layer before the removal.
In the conventional preparation method for gate electrodes by the lift-off process using the resist film, the more the gate pattern is to be subminiaturized, the more the deposited metal 16 quickly closes up the hole of the resist film as already shown in FIG. 4, so that the resultant gate electrode is relatively smaller in height with respect to the gate length (a width of the contacting portion of the gate electrode with the substrate), resulting in the problem that devices with the resultant gate electrode are poor in their properties due to increased gate resistance based on the reduced gate length.
The invention has been designed to overcome the above problem. An object of the invention is to provide a preparation method for gate electrode which allows the height of the gate electrode formed to be enlarged with respect to gate length and, in other words, enables the gate electrode to be prepared with reduced gate length without causing increase of gate resistance.
The inventor has made earnest study to reduce the gate length without causing increase of gate resistance and found that the reason of the gate electrode not being prepared with larger height is due to that the opening of the resist layer has such a cross-sectional shape as extending almost vertically or being reversely tapered toward the outer area from which a metal vapour is supplied under the metal deposition, so that the deposited metal is caused to quickly close up the hole of thee resist layer immediately after start of the deposition. The inventor also found that when the hole of the resist layer has such a cross-sectional shape as being normally tapered toward the outer area, it takes longer time for the deposited metal to close up the hole of the resist layer to thereby allow quartermicron gate electrode to be deposited with larger height.
However, in the case of fabrication by using a conventional resist film of single layer type, electron beam lithography is hard to provide the hole of the resist film with the cross-sectional shape as being normally tapered as aforesaid.